kernel/ATA: Read the CDROM's first sector using ATAPI PIO!!
Sadly, for some reason, DMA is not working right now. This is a problem, as PIO is inconvenient. But hey, it works for now!
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cc8450751c
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2fa11a5ae3
GPG Key ID:
B8A7D06E42258954
@ -4,6 +4,7 @@
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#include "arch/Timer.h"
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#include "arch/x86_64/IO.h"
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#include "memory/MemoryManager.h"
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#include <luna/CType.h>
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#include <luna/SafeArithmetic.h>
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#include <luna/Vector.h>
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@ -53,6 +54,15 @@ namespace ATA
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bool Controller::initialize()
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{
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u16 command_old = PCI::read16(m_device.address, PCI::Command);
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u16 command_new = command_old;
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command_new &= ~PCI::CMD_INTERRUPT_DISABLE;
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command_new |= PCI::CMD_IO_SPACE;
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command_new |= PCI::CMD_BUS_MASTER;
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if (command_new != command_old) PCI::write16(m_device.address, PCI::Command, command_new);
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if (!m_primary_channel.initialize()) return false;
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return m_secondary_channel.initialize();
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@ -121,7 +131,7 @@ namespace ATA
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void Channel::delay_400ns()
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{
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// FIXME: We should use kernel_sleep(), but it doesn't support nanosecond granularity.
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for (int i = 0; i < 14; i++) { read_control(ControlRegister::AltStatus); }
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for (int i = 0; i < 14; i++) { [[maybe_unused]] volatile u8 val = read_control(ControlRegister::AltStatus); }
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}
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void Channel::select(u8 drive)
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@ -140,35 +150,45 @@ namespace ATA
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{
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// FIXME: Read the Busmaster register to make sure the IRQ is for this channel.
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// FIXME: Also read it in case there was a DMA read error.
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if (m_current_drive < 2 && m_drives[m_current_drive]) m_drives[m_current_drive]->irq_handler();
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m_thread->wake_up();
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m_irq_called = true;
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if (m_thread) m_thread->wake_up();
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}
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void Channel::prepare_for_irq()
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{
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m_thread = Scheduler::current();
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m_irq_called = false;
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}
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void Channel::wait_for_irq()
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{
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m_thread = Scheduler::current();
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if (!m_irq_called) kernel_wait_for_event();
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kernel_wait_for_event();
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m_irq_called = false;
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}
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bool Channel::wait_for_irq_or_timeout(u64 timeout)
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{
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m_thread = Scheduler::current();
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if (!m_irq_called)
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{
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kernel_sleep(timeout);
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m_irq_called = false;
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return m_thread->sleep_ticks_left;
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}
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m_irq_called = false;
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return true;
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}
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bool Channel::wait_for_reg_set(Register reg, u8 value, u64 timeout)
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{
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u64 begin = Timer::ticks_ms();
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while (true)
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{
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u8 reg_value = read_register(reg);
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u8 reg_value = reg == Register::Status ? read_control(ControlRegister::AltStatus) : read_register(reg);
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if (reg_value & value) return true;
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if ((Timer::ticks_ms() - begin) >= timeout) return false;
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kernel_sleep(1);
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@ -180,7 +200,7 @@ namespace ATA
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u64 begin = Timer::ticks_ms();
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while (true)
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{
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u8 reg_value = read_register(reg);
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u8 reg_value = reg == Register::Status ? read_control(ControlRegister::AltStatus) : read_register(reg);
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if ((reg_value & value) == 0) return true;
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if ((Timer::ticks_ms() - begin) >= timeout) return false;
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kernel_sleep(1);
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@ -201,7 +221,7 @@ namespace ATA
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return err(EIO);
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}
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u8 status = read_register(Register::Status);
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u8 status = read_control(ControlRegister::AltStatus);
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if (status & SR_Error)
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{
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kwarnln("ata: An error occurred in drive %d:%d while waiting for data to become available", m_channel_index,
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@ -237,7 +257,7 @@ namespace ATA
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return false;
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}
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control_port_base_address = io_control.port();
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control_port_base_address = io_control.port() + 2;
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}
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else
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{
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@ -246,7 +266,7 @@ namespace ATA
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}
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m_io_base = io_base_address;
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m_control_base = control_port_base_address + 2;
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m_control_base = control_port_base_address;
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auto io_busmaster = m_controller->device().getBAR(4);
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if (!io_busmaster.is_iospace())
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@ -260,13 +280,7 @@ namespace ATA
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else
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m_interrupt_line = m_channel_index ? 15 : 14;
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bool ok = CPU::register_interrupt(m_interrupt_line, ::irq_handler, this);
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if (!ok)
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{
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kerrorln("ata: Failed to register IRQ handler for ATA channel %d (IRQ %d)", m_channel_index,
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m_interrupt_line);
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return false;
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}
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write_control(ControlRegister::DeviceControl, 0);
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for (u8 drive = 0; drive < 2; drive++)
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{
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@ -298,6 +312,26 @@ namespace ATA
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}
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}
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bool ok = CPU::register_interrupt(m_interrupt_line, ::irq_handler, this);
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if (!ok)
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{
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kerrorln("ata: Failed to register IRQ handler for ATA channel %d (IRQ %d)", m_channel_index,
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m_interrupt_line);
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return false;
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}
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for (u8 drive = 0; drive < 2; drive++)
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{
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if (m_drives[drive])
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{
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if (!m_drives[drive]->post_initialize())
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{
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m_drives[drive] = {};
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return false;
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}
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}
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}
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return true;
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}
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@ -397,6 +431,8 @@ namespace ATA
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m_dma_prdt_phys = frame.release_value();
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m_dma_prdt = (prdt_entry*)MMU::translate_physical_address(m_dma_prdt_phys);
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memset(m_dma_prdt, 0, ARCH_PAGE_SIZE);
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frame = MemoryManager::alloc_frame();
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if (frame.has_error() || frame.value() > 0xffffffff)
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{
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@ -406,6 +442,20 @@ namespace ATA
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m_dma_mem_phys = frame.release_value();
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m_dma_mem = (void*)MMU::translate_physical_address(m_dma_mem_phys);
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memset(const_cast<void*>(m_dma_mem), 0, ARCH_PAGE_SIZE);
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if (m_uses_dma)
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{
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auto cmd = m_channel->read_bm(BusmasterRegister::Command);
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cmd &= ~BMC_StartStop;
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m_channel->write_bm(BusmasterRegister::Command, cmd);
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}
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return true;
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}
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bool Drive::post_initialize()
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{
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if (m_is_atapi)
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{
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atapi_packet packet;
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@ -453,6 +503,14 @@ namespace ATA
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kinfoln("ata: Drive %d capacity information: Block Count=%lu, Block Size=%lu, Total Capacity=%lu",
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m_drive_index, m_block_count, m_block_size, total_capacity);
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char buf[2048];
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if (atapi_read_pio(0, buf, sizeof(buf)).has_error()) return false;
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char readable[2049];
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for (int i = 0; i < 2048; i++) { readable[i] = _iscntrl(buf[i]) ? '.' : buf[i]; }
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readable[2048] = 0;
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kinfoln("ata: Read first sector from CD-ROM: %s", readable);
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return true;
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}
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@ -500,6 +558,123 @@ namespace ATA
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return {};
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}
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#if 0
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Result<void> Drive::send_packet_atapi_dma(const atapi_packet* packet, void* out, u16 response_size)
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{
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check(m_uses_dma);
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m_channel->select(m_drive_index);
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kdbgln("have selected");
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// We use DMA here.
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m_channel->write_register(Register::Features, 0x01);
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m_channel->write_register(Register::LBAMiddle, 0);
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m_channel->write_register(Register::LBAHigh, 0);
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kdbgln("will do_dma_command");
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TRY(do_dma_command(CMD_Packet, response_size, false));
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TRY(m_channel->wait_until_ready());
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kdbgln("send atapi packet data");
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for (int j = 0; j < 6; j++) m_channel->write_data(packet->command_words[j]);
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kdbgln("do dma transfer");
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TRY(do_dma_transfer());
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memcpy(out, const_cast<void*>(m_dma_mem), response_size);
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return {};
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}
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Result<void> Drive::do_dma_command(u8 command, u16 count, bool write)
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{
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m_dma_prdt->address = (u32)m_dma_mem_phys;
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m_dma_prdt->count = count;
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m_dma_prdt->flags = END_OF_PRDT;
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kdbgln("ata: do_dma_command: phys=%x, command=%x, count=%u, write=%d", m_dma_prdt->address, command, count,
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write);
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m_channel->write_prdt_address((u32)m_dma_prdt_phys);
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auto status = m_channel->read_bm(BusmasterRegister::Status);
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status &= ~(BMS_DMAFailure | BMS_IRQPending);
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m_channel->write_bm(BusmasterRegister::Status, status);
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auto cmd = m_channel->read_bm(BusmasterRegister::Command);
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if (!write) cmd |= BMC_ReadWrite;
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else
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cmd &= ~BMC_ReadWrite;
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m_channel->write_bm(BusmasterRegister::Command, cmd);
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m_channel->prepare_for_irq();
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m_channel->write_register(Register::Command, command);
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cmd = m_channel->read_bm(BusmasterRegister::Command);
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cmd |= BMC_StartStop;
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m_channel->write_bm(BusmasterRegister::Command, cmd);
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m_channel->delay_400ns();
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return {};
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}
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Result<void> Drive::do_dma_transfer()
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{
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if (!m_channel->wait_for_irq_or_timeout(2000))
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{
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kwarnln("ata: Drive %d timed out (DMA)", m_drive_index);
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return err(EIO);
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}
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u8 status = m_channel->read_control(ControlRegister::AltStatus);
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kdbgln("ata: status after irq: %#x", status);
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m_channel->delay_400ns();
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auto cmd = m_channel->read_bm(BusmasterRegister::Command);
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cmd &= ~BMC_StartStop;
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m_channel->write_bm(BusmasterRegister::Command, cmd);
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status = m_channel->read_bm(BusmasterRegister::Status);
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m_channel->write_bm(BusmasterRegister::Status, status & ~(BMS_DMAFailure | BMS_IRQPending));
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if (status & BMS_DMAFailure)
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{
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kwarnln("ata: DMA failure while trying to read drive %d", m_drive_index);
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return err(EIO);
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}
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return {};
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}
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#endif
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Result<void> Drive::atapi_read_pio(u64 lba, void* out, usize size)
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{
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check(lba < m_block_count);
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check(size <= ARCH_PAGE_SIZE);
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atapi_packet read_packet;
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memset(&read_packet, 0, sizeof(read_packet));
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read_packet.command_bytes[0] = ATAPI_Read;
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read_packet.command_bytes[2] = (lba >> 0x18) & 0xff;
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read_packet.command_bytes[3] = (lba >> 0x10) & 0xff;
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read_packet.command_bytes[4] = (lba >> 0x08) & 0xff;
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read_packet.command_bytes[5] = (lba >> 0x00) & 0xff;
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read_packet.command_bytes[9] = (u8)(size / m_block_size);
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return send_packet_atapi_pio(&read_packet, out, (u16)size);
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}
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void Drive::irq_handler()
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{
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// Clear the IRQ flag.
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@ -510,5 +685,12 @@ namespace ATA
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u8 error = m_channel->read_register(Register::Error);
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(void)error;
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}
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if (m_uses_dma)
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{
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status = m_channel->read_bm(BusmasterRegister::Status);
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if (status & BMS_DMAFailure) { kwarnln("ata: DMA failure in irq"); }
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m_channel->write_bm(BusmasterRegister::Status, 4);
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}
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}
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}
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@ -68,6 +68,12 @@ namespace ATA
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BMS_DMAMode = 0x1
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};
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enum BusMasterCommand : u8
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{
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BMC_ReadWrite = 0x8,
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BMC_StartStop = 0x1,
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};
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struct ATAIdentify
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{
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u16 flags;
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@ -96,6 +102,7 @@ namespace ATA
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enum ATAPICommand : u8
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{
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ATAPI_ReadCapacity = 0x25,
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ATAPI_Read = 0xa8,
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};
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class Controller;
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@ -131,12 +138,22 @@ namespace ATA
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bool initialize();
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bool post_initialize();
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void irq_handler();
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private:
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bool identify_ata();
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Result<void> send_packet_atapi_pio(const atapi_packet* packet, void* out, u16 response_size);
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#if 0
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Result<void> send_packet_atapi_dma(const atapi_packet* packet, void* out, u16 response_size);
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Result<void> do_dma_command(u8 command, u16 count, bool write);
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Result<void> do_dma_transfer();
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#endif
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Result<void> atapi_read_pio(u64 lba, void* out, usize size);
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Channel* m_channel;
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@ -153,7 +170,7 @@ namespace ATA
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u64 m_block_count;
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u64 m_block_size;
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volatile prdt_entry* m_dma_prdt;
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prdt_entry* m_dma_prdt;
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u64 m_dma_prdt_phys;
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volatile void* m_dma_mem;
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u64 m_dma_mem_phys;
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@ -191,6 +208,8 @@ namespace ATA
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void delay_400ns();
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void prepare_for_irq();
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void wait_for_irq();
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bool wait_for_irq_or_timeout(u64 timeout);
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void irq_handler(Registers*);
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@ -208,12 +227,14 @@ namespace ATA
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KMutex<100> m_lock {};
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Thread* m_thread;
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Thread* m_thread { nullptr };
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u16 m_io_base;
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u16 m_control_base;
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u16 m_busmaster_base;
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bool m_irq_called { false };
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u8 m_current_drive = (u8)-1;
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SharedPtr<Drive> m_drives[2];
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