kernel/x86_64: Provide an alternate kernel stack for exceptions
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This avoids stack-related triple faults, hopefully. Closes #33.
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@ -1,6 +1,8 @@
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#include "arch/MMU.h"
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#include "arch/x86_64/CPU.h"
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#include <luna/CString.h>
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#include <luna/Check.h>
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#include <luna/Stack.h>
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#include <luna/Types.h>
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struct [[gnu::packed]] GDTR
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@ -75,10 +77,13 @@ static void set_tss_base(GDTEntry* tss1, HighGDTEntry* tss2, u64 addr)
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tss2->base_high = (u32)(addr >> 32);
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}
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static u8 alternate_stack[ARCH_PAGE_SIZE * 4];
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static void setup_tss()
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{
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memset(&task_state_segment, 0, sizeof(TSS));
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task_state_segment.iomap_base = sizeof(TSS);
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task_state_segment.ist[0] = Stack { (u64)alternate_stack, ARCH_PAGE_SIZE * 4 }.top();
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set_tss_base(&gdt.tss, &gdt.tss2, (u64)&task_state_segment);
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set_limit(&gdt.tss, sizeof(TSS) - 1);
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}
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@ -47,20 +47,21 @@ struct [[gnu::packed]] IDTR
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static_assert(sizeof(IDTR) == 10UL);
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static void idt_add_handler(short num, void* handler, u8 type_attr)
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static void idt_add_handler(short num, void* handler, u8 type_attr, u8 ist)
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{
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check(handler != nullptr);
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expect(num < 256, "IDT can only hold up to 256 entries");
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IDTEntry* const entry_for_handler = &idt[num];
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entry_for_handler->selector = 0x08;
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entry_for_handler->type_attr = type_attr;
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entry_for_handler->ist = ist;
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entry_for_handler->set_offset((u64)handler);
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}
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#define INT(x) extern "C" void _isr##x()
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#define TRAP(x) idt_add_handler(x, (void*)_isr##x, IDT_TA_TrapGate)
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#define IRQ(x) idt_add_handler(x, (void*)_isr##x, IDT_TA_InterruptGate)
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#define SYS(x) idt_add_handler(x, (void*)_isr##x, IDT_TA_UserCallableInterruptGate)
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#define TRAP(x) idt_add_handler(x, (void*)_isr##x, IDT_TA_TrapGate, 1)
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#define IRQ(x) idt_add_handler(x, (void*)_isr##x, IDT_TA_InterruptGate, 0)
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#define SYS(x) idt_add_handler(x, (void*)_isr##x, IDT_TA_UserCallableInterruptGate, 0)
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INT(0);
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INT(1);
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