apio
e9e7b22323
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continuous-integration/drone/pr Build is passing
The self directory, and the active directory. The active directory is the one the thread is currently using, and the self directory is the one the thread owns. This lets us keep track of both, which fixes ext2 executables crashing the system.
795 lines
24 KiB
C++
795 lines
24 KiB
C++
#include "arch/x86_64/disk/ATA.h"
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#include "Log.h"
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#include "arch/Serial.h"
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#include "arch/Timer.h"
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#include "arch/x86_64/IO.h"
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#include "fs/MBR.h"
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#include "memory/MemoryManager.h"
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#include <luna/Alignment.h>
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#include <luna/CType.h>
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#include <luna/SafeArithmetic.h>
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#include <luna/Vector.h>
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SharedPtr<ATA::Controller> g_controller;
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static void irq_handler(Registers* regs, void* ctx)
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{
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((ATA::Controller*)ctx)->irq_handler(regs);
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}
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static usize copy_ata_string(char* out, u16* in, usize size)
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{
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for (usize i = 0; i < size; i += 2)
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{
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u16 val = in[i / 2];
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out[i] = (u8)(val >> 8);
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out[i + 1] = (u8)(val & 0xff);
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}
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out[size + 1] = '\0';
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return size;
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}
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namespace ATA
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{
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Result<void> Controller::scan()
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{
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// FIXME: Propagate errors.
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PCI::scan(
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[](const PCI::Device& device) {
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if (!g_controller)
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{
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auto controller = adopt_shared_if_nonnull(new (std::nothrow) Controller(device)).release_value();
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kinfoln("ata: Found ATA controller on PCI bus (%x:%x:%x)", device.address.bus,
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device.address.function, device.address.slot);
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if (controller->initialize()) g_controller = controller;
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}
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},
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{ .klass = 1, .subclass = 1 });
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if (!g_controller) kwarnln("ata: No ATA controller found.");
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return {};
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}
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bool Controller::initialize()
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{
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u16 command_old = PCI::read16(m_device.address, PCI::Command);
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u16 command_new = command_old;
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command_new &= ~PCI::CMD_INTERRUPT_DISABLE;
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command_new |= PCI::CMD_IO_SPACE;
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command_new |= PCI::CMD_BUS_MASTER;
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if (command_new != command_old) PCI::write16(m_device.address, PCI::Command, command_new);
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if (!m_primary_channel.initialize()) return false;
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return m_secondary_channel.initialize();
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}
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void Controller::irq_handler(Registers* regs)
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{
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if (regs->irq == m_primary_channel.irq_line()) m_primary_channel.irq_handler(regs);
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if (regs->irq == m_secondary_channel.irq_line()) m_secondary_channel.irq_handler(regs);
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}
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Controller::Controller(const PCI::Device& device)
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: m_device(device), m_primary_channel(this, 0, {}), m_secondary_channel(this, 1, {})
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{
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}
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Channel::Channel(Controller* controller, u8 channel_index, Badge<Controller>)
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: m_controller(controller), m_channel_index(channel_index)
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{
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}
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u8 Channel::read_register(Register reg)
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{
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return IO::inb(m_io_base + (u16)reg);
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}
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u16 Channel::read_data()
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{
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return IO::inw(m_io_base + (u16)Register::Data);
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}
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void Channel::write_data(u16 value)
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{
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IO::outw(m_io_base + (u16)Register::Data, value);
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}
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void Channel::write_register(Register reg, u8 value)
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{
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IO::outb(m_io_base + (u16)reg, value);
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}
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u8 Channel::read_control(ControlRegister reg)
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{
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return IO::inb(m_control_base + (u16)reg);
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}
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void Channel::write_control(ControlRegister reg, u8 value)
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{
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IO::outb(m_control_base + (u16)reg, value);
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}
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u8 Channel::read_bm(BusmasterRegister reg)
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{
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return IO::inb(m_busmaster_base + (u16)reg);
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}
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void Channel::write_bm(BusmasterRegister reg, u8 value)
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{
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IO::outb(m_busmaster_base + (u16)reg, value);
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}
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u32 Channel::read_prdt_address()
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{
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return IO::inl(m_busmaster_base + (u16)BusmasterRegister::PRDTAddress);
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}
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void Channel::write_prdt_address(u32 value)
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{
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IO::outl(m_busmaster_base + (u16)BusmasterRegister::PRDTAddress, value);
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}
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void Channel::delay_400ns()
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{
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// FIXME: We should use kernel_sleep(), but it doesn't support nanosecond granularity.
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for (int i = 0; i < 14; i++) { [[maybe_unused]] volatile u8 val = read_control(ControlRegister::AltStatus); }
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}
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void Channel::select(u8 drive)
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{
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if (drive == m_current_drive) return;
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u8 value = (u8)(drive << 4) | 0xa0;
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write_register(Register::DriveSelect, value);
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delay_400ns();
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m_current_drive = drive;
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}
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void Channel::irq_handler(Registers*)
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{
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if (!(read_bm(BusmasterRegister::Status) & BMS_IRQPending)) return;
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if (m_current_drive < 2 && m_drives[m_current_drive]) m_drives[m_current_drive]->irq_handler();
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m_irq_called = true;
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if (m_thread) m_thread->wake_up();
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}
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void Channel::prepare_for_irq()
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{
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m_thread = Scheduler::current();
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m_irq_called = false;
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}
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void Channel::wait_for_irq()
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{
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if (!m_irq_called) kernel_wait_for_event();
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m_irq_called = false;
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}
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bool Channel::wait_for_irq_or_timeout(u64 timeout)
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{
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if (!m_irq_called)
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{
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kernel_sleep(timeout);
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m_irq_called = false;
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return m_thread->sleep_ticks_left;
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}
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m_irq_called = false;
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return true;
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}
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bool Channel::wait_for_reg_set(Register reg, u8 value, u64 timeout)
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{
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u64 begin = Timer::ticks_ms();
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while (true)
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{
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u8 reg_value = reg == Register::Status ? read_control(ControlRegister::AltStatus) : read_register(reg);
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if (reg_value & value) return true;
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if ((Timer::ticks_ms() - begin) >= timeout) return false;
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kernel_sleep(1);
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}
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}
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bool Channel::wait_for_reg_clear(Register reg, u8 value, u64 timeout)
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{
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u64 begin = Timer::ticks_ms();
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while (true)
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{
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u8 reg_value = reg == Register::Status ? read_control(ControlRegister::AltStatus) : read_register(reg);
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if ((reg_value & value) == 0) return true;
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if ((Timer::ticks_ms() - begin) >= timeout) return false;
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kernel_sleep(1);
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}
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}
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Result<void> Channel::wait_until_ready()
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{
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if (!wait_for_reg_clear(Register::Status, SR_Busy, 1000))
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{
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kwarnln("ata: Drive %d:%d timed out (BSY)", m_channel_index, m_current_drive);
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return err(EIO);
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}
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if (!wait_for_reg_set(Register::Status, SR_DataRequestReady | SR_Error, 1000))
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{
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kwarnln("ata: Drive %d:%d timed out (DRQ)", m_channel_index, m_current_drive);
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return err(EIO);
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}
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u8 status = read_control(ControlRegister::AltStatus);
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if (status & SR_Error)
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{
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kwarnln("ata: An error occurred in drive %d:%d while waiting for data to become available", m_channel_index,
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m_current_drive);
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return err(EIO);
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}
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return {};
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}
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bool Channel::initialize()
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{
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int offset = m_channel_index ? 2 : 0;
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m_is_pci_native_mode = m_controller->device().type.prog_if & (1 << offset);
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u16 control_port_base_address;
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u16 io_base_address;
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if (m_is_pci_native_mode)
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{
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auto io_base = m_controller->device().getBAR(m_channel_index ? 2 : 0);
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if (!io_base.is_iospace())
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{
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kwarnln("ata: Channel %d's IO base BAR is not in IO space", m_channel_index);
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return false;
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}
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io_base_address = io_base.port();
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auto io_control = m_controller->device().getBAR(m_channel_index ? 3 : 1);
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if (!io_control.is_iospace())
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{
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kwarnln("ata: Channel %d's control base BAR is not in IO space", m_channel_index);
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return false;
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}
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control_port_base_address = io_control.port() + 2;
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}
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else
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{
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io_base_address = m_channel_index ? 0x170 : 0x1f0;
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control_port_base_address = m_channel_index ? 0x376 : 0x3f6;
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}
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m_io_base = io_base_address;
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m_control_base = control_port_base_address;
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auto io_busmaster = m_controller->device().getBAR(4);
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if (!io_busmaster.is_iospace())
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{
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kwarnln("ata: Channel %d's busmaster base BAR is not in IO space", m_channel_index);
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return false;
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}
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m_busmaster_base = io_busmaster.port() + (u16)(m_channel_index * 8u);
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if (m_is_pci_native_mode) m_interrupt_line = PCI::read8(m_controller->device().address, PCI::InterruptLine);
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else
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m_interrupt_line = m_channel_index ? 15 : 14;
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write_control(ControlRegister::DeviceControl, 0);
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for (u8 drive = 0; drive < 2; drive++)
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{
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ScopedKMutexLock<100> lock(m_lock);
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select(drive);
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if (read_register(Register::Status) == 0)
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{
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// No drive on this slot.
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continue;
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}
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kinfoln("ata: Channel %d has a drive on slot %d!", m_channel_index, drive);
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auto rc = adopt_shared_if_nonnull(new (std::nothrow) Drive(this, drive, {}));
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if (rc.has_error())
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{
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kinfoln("ata: Failed to create drive object: %s", rc.error_string());
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return false;
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}
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m_drives[drive] = rc.release_value();
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if (!m_drives[drive]->initialize())
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{
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m_drives[drive] = {};
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return false;
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}
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}
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CPU::register_interrupt(m_interrupt_line, ::irq_handler, m_controller);
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for (u8 drive = 0; drive < 2; drive++)
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{
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if (m_drives[drive])
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{
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if (!m_drives[drive]->post_initialize())
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{
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m_drives[drive] = {};
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return false;
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}
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auto rc = ATADevice::create(m_drives[drive]);
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if (rc.has_error())
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{
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kwarnln("ata: Failed to register ATA drive %d:%d in DeviceRegistry", m_channel_index, drive);
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continue;
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}
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auto device = rc.release_value();
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MBR::identify(device);
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}
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}
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return true;
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}
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Drive::Drive(Channel* channel, u8 drive_index, Badge<Channel>) : m_channel(channel), m_drive_index(drive_index)
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{
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}
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bool Drive::identify_ata()
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{
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m_channel->write_register(Register::Command, m_is_atapi ? CMD_Identify_Packet : CMD_Identify);
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m_channel->delay_400ns();
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if (!m_channel->wait_for_reg_clear(Register::Status, SR_Busy, 1000))
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{
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kwarnln("ata: Drive %d timed out clearing SR_Busy (waited for 1000 ms)", m_drive_index);
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return false;
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}
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if (m_channel->read_register(Register::Status) & SR_Error)
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{
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u8 lbam = m_channel->read_register(Register::LBAMiddle);
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u8 lbah = m_channel->read_register(Register::LBAHigh);
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if ((lbam == 0x14 && lbah == 0xeb) || (lbam == 0x69 && lbah == 0x96))
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{
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if (!m_is_atapi)
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{
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kinfoln("ata: Drive %d is ATAPI, sending IDENTIFY_PACKET command", m_drive_index);
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m_is_atapi = true;
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return identify_ata();
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}
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}
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kwarnln("ata: IDENTIFY command for drive %d returned error", m_drive_index);
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return false;
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}
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if (!m_channel->wait_for_reg_set(Register::Status, SR_DataRequestReady | SR_Error, 1000))
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{
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kwarnln("ata: Drive %d timed out setting SR_DataRequestReady (waited for 1000 ms)", m_drive_index);
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return false;
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}
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u8 status = m_channel->read_register(Register::Status);
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if (status & SR_Error)
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{
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kwarnln("ata: IDENTIFY command for drive %d returned error", m_drive_index);
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return false;
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}
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for (usize i = 0; i < 256; i++)
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{
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u16 data = m_channel->read_data();
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m_identify_words[i] = data;
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}
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return true;
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}
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bool Drive::initialize()
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{
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m_channel->select(m_drive_index);
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m_channel->write_register(Register::SectorCount, 0);
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m_channel->write_register(Register::LBALow, 0);
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m_channel->write_register(Register::LBAMiddle, 0);
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m_channel->write_register(Register::LBAHigh, 0);
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if (!identify_ata()) return false;
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m_serial.set_length(copy_ata_string(m_serial.data(), &m_identify_words[10], SERIAL_LEN));
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m_revision.set_length(copy_ata_string(m_revision.data(), &m_identify_words[23], REVISION_LEN));
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m_model.set_length(copy_ata_string(m_model.data(), &m_identify_words[27], MODEL_LEN));
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m_serial.trim(" ");
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m_revision.trim(" ");
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m_model.trim(" ");
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kinfoln("ata: Drive IDENTIFY returned serial='%s', revision='%s' and model='%s'", m_serial.chars(),
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m_revision.chars(), m_model.chars());
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auto status = m_channel->read_bm(BusmasterRegister::Status);
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if (status & BMS_SimplexOnly)
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{
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kwarnln("ata: Drive %d will not use DMA because of simplex shenanigans", m_drive_index);
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m_uses_dma = false;
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}
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auto frame = MemoryManager::alloc_frame();
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if (frame.has_error() || frame.value() > 0xffffffff)
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{
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kwarnln("ata: Failed to allocate memory below the 32-bit limit for the PRDT");
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return false;
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}
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m_dma_prdt_phys = frame.release_value();
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m_dma_prdt = (prdt_entry*)MMU::translate_physical_address(m_dma_prdt_phys);
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memset(m_dma_prdt, 0, ARCH_PAGE_SIZE);
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frame = MemoryManager::alloc_frame();
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if (frame.has_error() || frame.value() > 0xffffffff)
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{
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kwarnln("ata: Failed to allocate memory below the 32-bit limit for DMA memory");
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return false;
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}
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m_dma_mem_phys = frame.release_value();
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m_dma_mem = (void*)MMU::translate_physical_address(m_dma_mem_phys);
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memset(const_cast<void*>(m_dma_mem), 0, ARCH_PAGE_SIZE);
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if (m_uses_dma)
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{
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auto cmd = m_channel->read_bm(BusmasterRegister::Command);
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cmd &= ~BMC_StartStop;
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m_channel->write_bm(BusmasterRegister::Command, cmd);
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}
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return true;
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}
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bool Drive::post_initialize()
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{
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if (m_is_atapi)
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{
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atapi_packet packet;
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memset(&packet, 0, sizeof(packet));
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packet.command_bytes[0] = ATAPI_ReadCapacity;
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atapi_read_capacity_reply reply;
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if (send_packet_atapi_pio(&packet, &reply, sizeof(reply)).has_error())
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{
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kwarnln("ata: Failed to send Read Capacity command to ATAPI drive");
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return false;
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}
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m_is_lba48 = true;
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// FIXME: This assumes the host machine is little-endian.
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u32 last_lba = __builtin_bswap32(reply.last_lba);
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u32 sector_size = __builtin_bswap32(reply.sector_size);
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m_block_count = last_lba + 1;
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m_block_size = sector_size;
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}
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else
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{
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if (m_identify_data.big_lba) m_is_lba48 = true;
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if (m_is_lba48) m_block_count = m_identify_data.sectors_48;
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else
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m_block_count = m_identify_data.sectors_28;
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// FIXME: Should we check for CHS?
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// FIXME: Maybe a different block size is in use? Detect that.
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m_block_size = 512;
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}
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u64 total_capacity;
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if (!safe_mul(m_block_count, m_block_size).try_set_value(total_capacity))
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{
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kwarnln("ata: Drive %d's total capacity is too large", m_drive_index);
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return false;
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}
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kinfoln("ata: Drive %d capacity information: Block Count=%lu, Block Size=%lu, Total Capacity=%lu",
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m_drive_index, m_block_count, m_block_size, total_capacity);
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return true;
|
|
}
|
|
|
|
Result<void> Drive::send_packet_atapi_pio(const atapi_packet* packet, void* out, u16 response_size)
|
|
{
|
|
u8* ptr = (u8*)out;
|
|
|
|
m_channel->select(m_drive_index);
|
|
|
|
// We use PIO here.
|
|
m_channel->write_register(Register::Features, 0x00);
|
|
|
|
m_channel->write_register(Register::LBAMiddle, (u8)(response_size & 0xff));
|
|
m_channel->write_register(Register::LBAHigh, (u8)(response_size >> 8));
|
|
|
|
m_channel->write_register(Register::Command, CMD_Packet);
|
|
|
|
m_channel->delay_400ns();
|
|
|
|
usize i = 0;
|
|
|
|
TRY(m_channel->wait_until_ready());
|
|
|
|
for (int j = 0; j < 6; j++) m_channel->write_data(packet->command_words[j]);
|
|
|
|
while (i < response_size)
|
|
{
|
|
TRY(m_channel->wait_until_ready());
|
|
|
|
usize byte_count =
|
|
m_channel->read_register(Register::LBAHigh) << 8 | m_channel->read_register(Register::LBAMiddle);
|
|
usize word_count = byte_count / 2;
|
|
|
|
while (word_count--)
|
|
{
|
|
u16 value = m_channel->read_data();
|
|
ptr[0] = (u8)(value & 0xff);
|
|
ptr[1] = (u8)(value >> 8);
|
|
ptr += 2;
|
|
}
|
|
|
|
i += byte_count;
|
|
}
|
|
|
|
return {};
|
|
}
|
|
|
|
#if 0
|
|
|
|
Result<void> Drive::send_packet_atapi_dma(const atapi_packet* packet, void* out, u16 response_size)
|
|
{
|
|
check(m_uses_dma);
|
|
|
|
m_channel->select(m_drive_index);
|
|
|
|
kdbgln("have selected");
|
|
|
|
// We use DMA here.
|
|
m_channel->write_register(Register::Features, 0x01);
|
|
|
|
m_channel->write_register(Register::LBAMiddle, 0);
|
|
m_channel->write_register(Register::LBAHigh, 0);
|
|
|
|
kdbgln("will do_dma_command");
|
|
|
|
TRY(do_dma_command(CMD_Packet, response_size, false));
|
|
|
|
TRY(m_channel->wait_until_ready());
|
|
|
|
kdbgln("send atapi packet data");
|
|
|
|
for (int j = 0; j < 6; j++) m_channel->write_data(packet->command_words[j]);
|
|
|
|
kdbgln("do dma transfer");
|
|
|
|
TRY(do_dma_transfer());
|
|
|
|
memcpy(out, const_cast<void*>(m_dma_mem), response_size);
|
|
|
|
return {};
|
|
}
|
|
|
|
Result<void> Drive::do_dma_command(u8 command, u16 count, bool write)
|
|
{
|
|
m_dma_prdt->address = (u32)m_dma_mem_phys;
|
|
m_dma_prdt->count = count;
|
|
m_dma_prdt->flags = END_OF_PRDT;
|
|
|
|
kdbgln("ata: do_dma_command: phys=%x, command=%x, count=%u, write=%d", m_dma_prdt->address, command, count,
|
|
write);
|
|
|
|
m_channel->write_prdt_address((u32)m_dma_prdt_phys);
|
|
|
|
auto status = m_channel->read_bm(BusmasterRegister::Status);
|
|
status &= ~(BMS_DMAFailure | BMS_IRQPending);
|
|
m_channel->write_bm(BusmasterRegister::Status, status);
|
|
|
|
auto cmd = m_channel->read_bm(BusmasterRegister::Command);
|
|
if (!write) cmd |= BMC_ReadWrite;
|
|
else
|
|
cmd &= ~BMC_ReadWrite;
|
|
m_channel->write_bm(BusmasterRegister::Command, cmd);
|
|
|
|
m_channel->prepare_for_irq();
|
|
|
|
m_channel->write_register(Register::Command, command);
|
|
|
|
cmd = m_channel->read_bm(BusmasterRegister::Command);
|
|
cmd |= BMC_StartStop;
|
|
m_channel->write_bm(BusmasterRegister::Command, cmd);
|
|
|
|
m_channel->delay_400ns();
|
|
|
|
return {};
|
|
}
|
|
|
|
Result<void> Drive::do_dma_transfer()
|
|
{
|
|
if (!m_channel->wait_for_irq_or_timeout(2000))
|
|
{
|
|
kwarnln("ata: Drive %d timed out (DMA)", m_drive_index);
|
|
return err(EIO);
|
|
}
|
|
|
|
u8 status = m_channel->read_control(ControlRegister::AltStatus);
|
|
kdbgln("ata: status after irq: %#x", status);
|
|
|
|
m_channel->delay_400ns();
|
|
|
|
auto cmd = m_channel->read_bm(BusmasterRegister::Command);
|
|
cmd &= ~BMC_StartStop;
|
|
m_channel->write_bm(BusmasterRegister::Command, cmd);
|
|
|
|
status = m_channel->read_bm(BusmasterRegister::Status);
|
|
m_channel->write_bm(BusmasterRegister::Status, status & ~(BMS_DMAFailure | BMS_IRQPending));
|
|
|
|
if (status & BMS_DMAFailure)
|
|
{
|
|
kwarnln("ata: DMA failure while trying to read drive %d", m_drive_index);
|
|
return err(EIO);
|
|
}
|
|
|
|
return {};
|
|
}
|
|
|
|
#endif
|
|
|
|
Result<void> Drive::atapi_read_pio(u64 lba, void* out, usize size)
|
|
{
|
|
check(lba < m_block_count);
|
|
check(size <= ARCH_PAGE_SIZE);
|
|
|
|
atapi_packet read_packet;
|
|
memset(&read_packet, 0, sizeof(read_packet));
|
|
read_packet.command_bytes[0] = ATAPI_Read;
|
|
read_packet.command_bytes[2] = (lba >> 0x18) & 0xff;
|
|
read_packet.command_bytes[3] = (lba >> 0x10) & 0xff;
|
|
read_packet.command_bytes[4] = (lba >> 0x08) & 0xff;
|
|
read_packet.command_bytes[5] = (lba >> 0x00) & 0xff;
|
|
read_packet.command_bytes[9] = (u8)(size / m_block_size);
|
|
|
|
return send_packet_atapi_pio(&read_packet, out, (u16)size);
|
|
}
|
|
|
|
Result<void> Drive::read_lba(u64 lba, void* out, usize nblocks)
|
|
{
|
|
const usize blocks_per_page = ARCH_PAGE_SIZE / m_block_size;
|
|
if (m_is_atapi)
|
|
{
|
|
while (nblocks > blocks_per_page)
|
|
{
|
|
TRY(atapi_read_pio(lba, out, ARCH_PAGE_SIZE));
|
|
lba += blocks_per_page;
|
|
nblocks -= blocks_per_page;
|
|
out = offset_ptr(out, ARCH_PAGE_SIZE);
|
|
}
|
|
return atapi_read_pio(lba, out, nblocks * m_block_size);
|
|
}
|
|
else
|
|
todo();
|
|
}
|
|
|
|
void Drive::irq_handler()
|
|
{
|
|
// Clear the IRQ flag.
|
|
u8 status = m_channel->read_register(Register::Status);
|
|
|
|
if (status & SR_Error)
|
|
{
|
|
u8 error = m_channel->read_register(Register::Error);
|
|
(void)error;
|
|
}
|
|
|
|
if (m_uses_dma)
|
|
{
|
|
status = m_channel->read_bm(BusmasterRegister::Status);
|
|
if (status & BMS_DMAFailure) { kwarnln("ata: DMA failure in irq"); }
|
|
m_channel->write_bm(BusmasterRegister::Status, 4);
|
|
}
|
|
}
|
|
}
|
|
|
|
static u32 next_minor = 0;
|
|
|
|
Result<String> ATA::Drive::create_drive_name(SharedPtr<ATA::Drive> drive)
|
|
{
|
|
static u32 cd_index = 0;
|
|
static u32 sd_index = 0;
|
|
|
|
return String::format("%s%d"_sv, drive->m_is_atapi ? "cd" : "sd", drive->m_is_atapi ? cd_index++ : sd_index++);
|
|
}
|
|
|
|
Result<SharedPtr<Device>> ATADevice::create(SharedPtr<ATA::Drive> drive)
|
|
{
|
|
auto device = TRY(adopt_shared_if_nonnull(new (std::nothrow) ATADevice()));
|
|
device->m_drive = drive;
|
|
device->m_device_path = TRY(ATA::Drive::create_drive_name(drive));
|
|
TRY(DeviceRegistry::register_special_device(DeviceRegistry::Disk, next_minor++, device, 0400));
|
|
return (SharedPtr<Device>)device;
|
|
}
|
|
|
|
Result<u64> ATADevice::read(u8* buf, usize offset, usize size) const
|
|
{
|
|
if (size == 0) return 0;
|
|
|
|
if (offset > m_drive->capacity()) return 0;
|
|
if (offset + size > m_drive->capacity()) size = m_drive->capacity() - offset;
|
|
|
|
usize length = size;
|
|
|
|
auto block_size = m_drive->block_size();
|
|
|
|
ScopedKMutexLock<100> lock(m_drive->channel()->lock());
|
|
|
|
// FIXME: Don't always allocate this if we don't need it.
|
|
auto* temp = TRY(make_array<u8>(block_size));
|
|
auto guard = make_scope_guard([temp] { delete[] temp; });
|
|
|
|
if (offset % block_size)
|
|
{
|
|
// The size we need to read to round up to a block.
|
|
usize extra_size = block_size - (offset % block_size);
|
|
// Maybe we don't even want enough to get to the next block?
|
|
if (extra_size > size) extra_size = size;
|
|
|
|
TRY(m_drive->read_lba(offset / block_size, temp, 1));
|
|
memcpy(buf, temp + (offset % block_size), extra_size);
|
|
offset += extra_size;
|
|
size -= extra_size;
|
|
buf += extra_size;
|
|
}
|
|
|
|
while (size >= ARCH_PAGE_SIZE)
|
|
{
|
|
TRY(m_drive->read_lba(offset / block_size, buf, ARCH_PAGE_SIZE / block_size));
|
|
offset += ARCH_PAGE_SIZE;
|
|
size -= ARCH_PAGE_SIZE;
|
|
buf += ARCH_PAGE_SIZE;
|
|
}
|
|
|
|
while (size >= block_size)
|
|
{
|
|
TRY(m_drive->read_lba(offset / block_size, buf, 1));
|
|
offset += block_size;
|
|
size -= block_size;
|
|
buf += block_size;
|
|
}
|
|
|
|
if (size)
|
|
{
|
|
TRY(m_drive->read_lba(offset / block_size, temp, 1));
|
|
memcpy(buf, temp, size);
|
|
}
|
|
|
|
return length;
|
|
}
|