304 lines
8.9 KiB
C++
304 lines
8.9 KiB
C++
#include "arch/x86_64/disk/ATA.h"
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#include "Log.h"
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#include "arch/Serial.h"
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#include "arch/Timer.h"
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#include "arch/x86_64/IO.h"
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#include <luna/Vector.h>
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SharedPtr<ATA::Controller> g_controller;
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static void irq_handler(Registers* regs, void* ctx)
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{
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((ATA::Channel*)ctx)->irq_handler(regs);
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}
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namespace ATA
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{
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Result<void> Controller::scan()
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{
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// FIXME: Propagate errors.
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PCI::scan(
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[](const PCI::Device& device) {
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if (!g_controller)
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{
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auto controller = adopt_shared_if_nonnull(new (std::nothrow) Controller(device)).release_value();
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kinfoln("ata: Found ATA controller on PCI bus (%x:%x:%x)", device.address.bus,
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device.address.function, device.address.slot);
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if (controller->initialize()) g_controller = controller;
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}
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},
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{ .klass = 1, .subclass = 1 });
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if (!g_controller) kwarnln("ata: No ATA controller found.");
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return {};
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}
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bool Controller::initialize()
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{
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if (!m_primary_channel.initialize()) return false;
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return m_secondary_channel.initialize();
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}
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Controller::Controller(const PCI::Device& device)
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: m_device(device), m_primary_channel(this, 0, {}), m_secondary_channel(this, 1, {})
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{
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}
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Channel::Channel(Controller* controller, u8 channel_index, Badge<Controller>)
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: m_controller(controller), m_channel_index(channel_index)
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{
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}
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u8 Channel::read_register(Register reg)
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{
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return IO::inb(m_io_base + (u16)reg);
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}
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u16 Channel::read_data()
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{
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return IO::inw(m_io_base + (u16)Register::Data);
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}
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void Channel::write_register(Register reg, u8 value)
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{
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IO::outb(m_io_base + (u16)reg, value);
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}
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u8 Channel::read_control(ControlRegister reg)
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{
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return IO::inb(m_control_base + (u16)reg);
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}
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void Channel::write_control(ControlRegister reg, u8 value)
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{
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IO::outb(m_control_base + (u16)reg, value);
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}
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void Channel::delay_400ns()
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{
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// FIXME: We should use kernel_sleep(), but it doesn't support nanosecond granularity.
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for (int i = 0; i < 14; i++) { read_control(ControlRegister::AltStatus); }
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}
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void Channel::select(u8 drive)
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{
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if (drive == m_current_drive) return;
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u8 value = (drive << 4) | 0xa0;
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write_register(Register::DriveSelect, value);
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delay_400ns();
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m_current_drive = drive;
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}
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void Channel::irq_handler(Registers*)
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{
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// FIXME: Read the Busmaster register to make sure the IRQ is for this channel.
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// FIXME: Also read it in case there was a DMA read error.
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if (m_current_drive < 2 && m_drives[m_current_drive]) m_drives[m_current_drive]->irq_handler();
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m_thread->wake_up();
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}
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void Channel::wait_for_irq()
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{
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m_thread = Scheduler::current();
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kernel_wait_for_event();
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}
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bool Channel::wait_for_reg_set(Register reg, u8 value, u64 timeout)
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{
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u64 begin = Timer::ticks_ms();
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while (true)
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{
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u8 reg_value = read_register(reg);
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if (reg_value & value) return true;
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if ((Timer::ticks_ms() - begin) >= timeout) return false;
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kernel_sleep(1);
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}
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}
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bool Channel::wait_for_reg_clear(Register reg, u8 value, u64 timeout)
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{
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u64 begin = Timer::ticks_ms();
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while (true)
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{
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u8 reg_value = read_register(reg);
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if ((reg_value & value) == 0) return true;
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if ((Timer::ticks_ms() - begin) >= timeout) return false;
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kernel_sleep(1);
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}
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}
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bool Channel::initialize()
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{
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int offset = m_channel_index ? 2 : 0;
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m_is_pci_native_mode = m_controller->device().type.prog_if & (1 << offset);
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u32 control_port_base_address;
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u32 io_base_address;
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if (m_is_pci_native_mode)
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{
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// FIXME: Properly decode BARs.
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io_base_address = PCI::read32(m_controller->device().address, m_channel_index ? PCI::BAR2 : PCI::BAR0);
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control_port_base_address =
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PCI::read32(m_controller->device().address, m_channel_index ? PCI::BAR3 : PCI::BAR1);
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}
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else
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{
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io_base_address = m_channel_index ? 0x170 : 0x1f0;
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control_port_base_address = m_channel_index ? 0x376 : 0x3f6;
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}
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m_io_base = (u16)io_base_address;
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m_control_base = (u16)control_port_base_address + 2;
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if (m_is_pci_native_mode) m_interrupt_line = PCI::read8(m_controller->device().address, PCI::InterruptLine);
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else
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m_interrupt_line = m_channel_index ? 15 : 14;
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bool ok = CPU::register_interrupt(m_interrupt_line, ::irq_handler, this);
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if (!ok)
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{
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kerrorln("ata: Failed to register IRQ handler for ATA channel %d (IRQ %d)", m_channel_index,
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m_interrupt_line);
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return false;
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}
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for (u8 drive = 0; drive < 2; drive++)
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{
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ScopedKMutexLock<100> lock(m_lock);
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select(drive);
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if (read_register(Register::Status) == 0)
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{
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// No drive on this slot.
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continue;
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}
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kinfoln("ata: Channel %d has a drive on slot %d!", m_channel_index, drive);
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auto rc = adopt_shared_if_nonnull(new (std::nothrow) Drive(this, drive, {}));
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if (rc.has_error())
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{
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kinfoln("ata: Failed to create drive object: %s", rc.error_string());
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return false;
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}
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m_drives[drive] = rc.release_value();
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if (!m_drives[drive]->initialize())
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{
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m_drives[drive] = {};
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return false;
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}
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}
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return true;
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}
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Drive::Drive(Channel* channel, u8 drive_index, Badge<Channel>) : m_channel(channel), m_drive_index(drive_index)
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{
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}
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bool Drive::identify_ata()
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{
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m_channel->write_register(Register::Command, m_is_atapi ? CMD_Identify_Packet : CMD_Identify);
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m_channel->delay_400ns();
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if (!m_channel->wait_for_reg_clear(Register::Status, SR_Busy, 1000))
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{
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kwarnln("ata: Drive %d timed out clearing SR_Busy (waited for 1000 ms)", m_drive_index);
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return false;
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}
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if (m_channel->read_register(Register::Status) & SR_Error)
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{
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u8 lbam = m_channel->read_register(Register::LBAMiddle);
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u8 lbah = m_channel->read_register(Register::LBAHigh);
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if ((lbam == 0x14 && lbah == 0xeb) || (lbam == 0x69 && lbah == 0x96))
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{
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if (!m_is_atapi)
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{
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kinfoln("ata: Drive %d is ATAPI, sending IDENTIFY_PACKET command", m_drive_index);
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m_is_atapi = true;
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return identify_ata();
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}
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}
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kwarnln("ata: IDENTIFY command for drive %d returned error", m_drive_index);
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return false;
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}
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if (!m_channel->wait_for_reg_set(Register::Status, SR_DataRequestReady | SR_Error, 1000))
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{
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kwarnln("ata: Drive %d timed out setting SR_DataRequestReady (waited for 1000 ms)", m_drive_index);
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return false;
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}
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u8 status = m_channel->read_register(Register::Status);
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if (status & SR_Error)
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{
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kwarnln("ata: IDENTIFY command for drive %d returned error", m_drive_index);
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return false;
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}
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for (usize i = 0; i < 256; i++)
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{
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u16 data = m_channel->read_data();
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m_identify_words[i] = data;
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}
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return true;
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}
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bool Drive::initialize()
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{
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m_channel->select(m_drive_index);
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m_channel->write_register(Register::SectorCount, 0);
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m_channel->write_register(Register::LBALow, 0);
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m_channel->write_register(Register::LBAMiddle, 0);
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m_channel->write_register(Register::LBAHigh, 0);
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if (!identify_ata()) return false;
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m_serial = StringView::from_fixed_size_cstring((const char*)&m_identify_words[10], SERIAL_LEN);
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m_revision = StringView::from_fixed_size_cstring((const char*)&m_identify_words[23], REVISION_LEN);
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m_model = StringView::from_fixed_size_cstring((const char*)&m_identify_words[27], MODEL_LEN);
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m_serial.trim(" ");
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m_revision.trim(" ");
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m_model.trim(" ");
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kinfoln("ata: Drive IDENTIFY returned serial='%s', revision='%s' and model='%s'", m_serial.chars(),
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m_revision.chars(), m_model.chars());
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return true;
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}
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void Drive::irq_handler()
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{
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// Clear the IRQ flag.
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u8 status = m_channel->read_register(Register::Status);
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if (status & SR_Error)
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{
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u8 error = m_channel->read_register(Register::Error);
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(void)error;
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}
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}
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}
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