134 lines
3.7 KiB
C++
134 lines
3.7 KiB
C++
#include "arch/x86_64/disk/ATA.h"
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#include "Log.h"
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#include "arch/x86_64/IO.h"
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#include <luna/Vector.h>
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SharedPtr<ATA::Controller> g_controller;
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namespace ATA
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{
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Result<void> Controller::scan()
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{
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// FIXME: Propagate errors.
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PCI::scan(
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[](const PCI::Device& device) {
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if (!g_controller)
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{
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auto controller = adopt_shared_if_nonnull(new (std::nothrow) Controller(device)).release_value();
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kinfoln("ata: Found ATA controller on PCI bus (%x:%x:%x)", device.address.bus,
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device.address.function, device.address.slot);
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if (controller->initialize()) g_controller = controller;
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}
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},
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{ .klass = 1, .subclass = 1 });
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if (!g_controller) kwarnln("ata: No ATA controller found.");
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return {};
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}
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bool Controller::initialize()
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{
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if (!m_primary_channel.initialize()) return false;
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return m_secondary_channel.initialize();
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}
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Controller::Controller(const PCI::Device& device)
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: m_device(device), m_primary_channel(this, 0, {}), m_secondary_channel(this, 1, {})
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{
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}
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Channel::Channel(Controller* controller, u8 channel_index, Badge<Controller>)
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: m_controller(controller), m_channel_index(channel_index)
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{
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}
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u8 Channel::read_register(Register reg)
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{
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return IO::inb(m_io_base + (u16)reg);
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}
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void Channel::write_register(Register reg, u8 value)
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{
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IO::outb(m_io_base + (u16)reg, value);
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}
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u8 Channel::read_control(ControlRegister reg)
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{
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return IO::inb(m_control_base + (u16)reg);
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}
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void Channel::write_control(ControlRegister reg, u8 value)
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{
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IO::outb(m_control_base + (u16)reg, value);
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}
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void Channel::delay_400ns()
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{
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read_control(ControlRegister::AltStatus);
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read_control(ControlRegister::AltStatus);
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read_control(ControlRegister::AltStatus);
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read_control(ControlRegister::AltStatus);
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}
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void Channel::select(u8 drive)
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{
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if (drive == m_current_drive) return;
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u8 value = (drive << 4) | 0xa0;
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write_register(Register::DriveSelect, value);
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delay_400ns();
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m_current_drive = drive;
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}
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bool Channel::initialize()
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{
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int offset = m_channel_index ? 2 : 0;
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m_is_pci_native_mode = m_controller->device().type.prog_if & (1 << offset);
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u32 control_port_base_address;
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u32 io_base_address;
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if (m_is_pci_native_mode)
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{
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// FIXME: Properly decode BARs.
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io_base_address = PCI::read32(m_controller->device().address, m_channel_index ? PCI::BAR2 : PCI::BAR0);
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control_port_base_address =
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PCI::read32(m_controller->device().address, m_channel_index ? PCI::BAR3 : PCI::BAR1);
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}
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else
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{
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io_base_address = m_channel_index ? 0x170 : 0x1f0;
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control_port_base_address = m_channel_index ? 0x376 : 0x3f6;
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}
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m_io_base = (u16)io_base_address;
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m_control_base = (u16)control_port_base_address + 2;
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if (m_is_pci_native_mode) m_interrupt_line = PCI::read8(m_controller->device().address, PCI::InterruptLine);
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else
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m_interrupt_line = m_channel_index ? 15 : 14;
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for (u8 drive = 0; drive < 2; drive++)
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{
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ScopedKMutexLock<100> lock(m_lock);
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select(drive);
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if (read_register(Register::Status) == 0)
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{
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// No drive on this slot.
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continue;
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}
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kinfoln("ata: Channel %d has a drive on slot %d!", m_channel_index, drive);
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}
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return true;
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}
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}
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